1. Field
Certain aspects of the present disclosure generally relate to signal processing and, more particularly, to designing an analog-to-digital converter (ADC) for digitizing and communicating biomedical signals.
2. Background
Biomedical signals, such as electrocardiograms (ECG) and electroencephalograms (EEG), are typically sampled at hundreds of Hz. There is a growing interest in designing low power systems to record and wirelessly transmit such signals from a subject to a gateway or a receiver. This may require the design of low power electronics for analog front-ends.
Successive approximation register (SAR) based Analog-to-Digital Converters (ADCs) are popular in biomedical data acquisition systems due to their medium to high resolution and low power consumption. Lowering power consumption of such systems is desirable since these tend to be battery powered and need to last long periods without recharging. Charge redistribution SAR ADCs are commonly used for this application. One approach to further lowering power consumption can be to develop new ADC architectures based on characteristics of the biomedical signal.
Conventional n-bit SAR ADCs may require n cycles to complete the signal digitization. Using a binary search algorithm, the ADC may convert the input signal one bit at a time from a Most Significant Bit (MSB) to a Least Significant Bit (LSB). However, higher bits of a slowly varying signal may tend to change very infrequently; therefore a large fraction of the conversion cycles may be wasted. One way to address this issue can be to utilize the conventional SAR with modified digital logic, which may start the conversion process from a new point for each sample based on the previous value of the signal, and may choose the depth of the search tree based on the current rate of change of the signal. While this architecture may lead to power reductions, it may cause an increase in area and may not reduce the effect of DC offsets.